TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
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3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with
exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on
page 71 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable
(the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.
Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to
Bootcfg MMRs.
The kicker mechanism is unlocked by the ROM code. Do not write any other different values afterward to these
registers because that will lock the kicker mechanism and block any writes to Bootcfg registers.
3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6 .
Figure 3-4
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
18
17
NMI1
R-0
16
NMI0
R-0
15
2
1
0
Reserved
Reserved
LR1
R-0
LR0
R-0
R, +0000 0000
R, +0000 0000
Legend: R = Read only; -n = value after reset;
Table 3-6
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
Bit
Field
Description
Reserved
31-18 Reserved
17
16
15-2
1
NMI1
NMI0
CorePac1 in NMI
CorePac0 in NMI
Reserved
LR1
Reserved
CorePac1 in Local Reset
CorePac0 in Local Reset
0
LR0
End of Table 3-6
3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7 .
Figure 3-5
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
18
17
16
15
2
1
0
Reserved
NMI1
WC,+0
NMI0
WC,+0
Reserved
LR1
LR0
R, +0000 0000
R, +0000 0000
WC,+0
WC,+0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
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Device Configuration 77
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