TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Figure 7-36
I2C Receive Timings
11
9
SDA
SCL
8
6
14
4
10
13
5
1
3
12
7
2
3
Stop
Start
Repeated
Start
Stop
Table 7-65
I2C Switching Characteristics (1)
(see Figure 7-37)
Standard Mode
Fast Mode
Min
No.
Parameter
Min
Max
Max Unit
16
17
tc(SCL)
Cycle time, SCL
10
2.5
ms
ms
Setup time, SCL high to SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
18
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
th(SDAL-SCLL)
ms
19
20
21
22
23
24
25
26
27
28
29
tw(SCLL)
tw(SCLH)
td(SDAV-SDLH)
tv(SDLL-SDAV)
tw(SDAH)
tr(SDA)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
ms
ms
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
250
0
ns
0.9 ms
ms
4.7
1.3
(1)
1000
1000
300
20 + 0.1Cb
300 ns
300 ns
300 ns
300 ns
ms
(1)
(1)
(1)
tr(SCL)
Rise time, SCL
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
10
10 pF
End of Table 7-65
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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Peripheral Information and Electrical Specifications 195
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