TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Figure 7-35 shows a block diagram of the I2C module.
Figure 7-35
I2C Module Block Diagram
I2C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
I2CPSC
Control
Bit Clock
Own
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
Generator
Address
SCL
Noise
Filter
I2C Clock
I2CCLKH
I2CCLKL
Slave
Address
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
Filter
I2C Data
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
Interrupt
Vector
I2CRSR
I2CIVR
Receive
Shift
Shading denotes control/status registers.
7.12.2 I2C Peripheral Register Description(s)
Table 7-63
I2C Registers (Part 1 of 2)
Hex Address Range
0253 0000
0253 0004
0253 0008
0253 000C
0253 0010
0253 0014
0253 0018
0253 001C
0253 0020
0253 0024
0253 0028
0253 002C
0253 0030
Register
ICOAR
ICIMR
Register Name
I2C Own Address Register
I2C Interrupt Mask/Status Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
Copyright 2012 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 193
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