TMS320C6672
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS708C—February 2012
www.ti.com
Table 7-40
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 2 of 5)
Input Event # on CIC System Interrupt
Description
4
GPINT12
GPIO interrupt
5
GPINT13
GPIO interrupt
6
GPINT14
GPIO interrupt
7
GPINT15
GPIO interrupt
8
TETBHFULLINT
TETBFULLINT
System TETB is half full
System TETB is full
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
TETBACQINT
System TETB acquisition has been completed
TETB0 is half full
TETBHFULLINT0
TETBFULLINT0
TETBACQINT0
TETBHFULLINT1
TETBFULLINT1
TETBACQINT1
Reserved
TETB0 is full
TETB0 acquisition has been completed
TETB1 is half full
TETB1 is full
TETB1 acquisition has been completed
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QM_INT_HIGH_16
QM_INT_HIGH_17
QM_INT_HIGH_18
QM_INT_HIGH_19
QM_INT_HIGH_20
QM_INT_HIGH_21
QM_INT_HIGH_22
QM_INT_HIGH_23
QM_INT_HIGH_24
QM_INT_HIGH_25
QM_INT_HIGH_26
QM_INT_HIGH_27
QM_INT_HIGH_28
QM_INT_HIGH_29
QM_INT_HIGH_30
QM_INT_HIGH_31
MDIO_LINK_INTR0
MDIO_LINK_INTR1
MDIO_USER_INTR0
MDIO_USER_INTR0
MISC_INTR
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MISC interrupt
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
Reserved
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Peripheral Information and Electrical Specifications 165
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