TMDS361
SLLS919–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
T0395-01
Figure 38. I2C Acknowledge
1
2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
Stop
Acknowledge
MSB
Acknowledge
Slave Address
Data
T0396-01
Figure 39. I2C Address, Data Cycle(s), and Stop
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 40 and Figure 41.
Note that the TMDS361 allows multiple write transfers to occur. See the Example – Writing to the TMDS361
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 42 and Figure 43.
See the Example – Reading from the TMDS361 section for more information.
From Receiver
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
W
A
Data
A
Data
A
P
S
Slave Address
From Transmitter
R0007-01
Figure 40. I2C Write Cycle
32
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