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TMDS361 参数 Datasheet PDF下载

TMDS361图片预览
型号: TMDS361
PDF下载: 下载PDF文件 查看货源
内容描述: 1080 - 深色3比1 HDMI / DVI开关,具有自适应均衡 [1080p - Deep Color 3-to-1 HDMI/DVI Switch with Adaptive Equalization]
分类和应用: 开关
文件页数/大小: 42 页 / 2118 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMDS361  
www.ti.com ............................................................................................................................................................................................ SLLS919DECEMBER 2008  
Step 6  
0
I2C stop (master)  
P
Step 6 is optional.  
TMDS361 Read Phase 2  
Step 7  
0
I2C start (master)  
S
Step 8  
7
6
5
4
3
2
1
0
I2C general address (master)  
0
1
0
1
1
0
0
1
Step 9  
8
I2C acknowledge (slave)  
A
Step 10  
7
6
5
4
3
2
1
0
I2C read data (slave)  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Data  
Where data is determined by the logic values contained in the internal registers.  
Step 11A  
8
I2C acknowledge (master)  
A
If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.  
Step 11B  
8
I2C not acknowledge (master)  
A
Step 12  
0
I2C stop (master)  
P
Table 8. I2C Register 0x01 Lookup Table  
BIT  
VALUE STATE  
DEFAULT  
DESCRIPTION  
7:6  
Bit 7  
Bit 6  
Port Select I2C Mode  
1
1
X
Port 1 is selected as the active port; HPD on non-selected ports is low. HPD1 can go low, high  
or high-Z; there is no external 1-kpullup resistor to 5 V.  
1
0
0
0
Port 2 is selected as the active port; HPD on non-selected ports is low. HPD2 can go low, high  
or high-Z; there is no external 1-kpullup resistor to 5 V.  
Port 3 is selected as the active port; HPD on non-selected ports is low. HPD3 can go low, high  
or high-Z; there is no external 1-kpullup resistor to 5 V.  
0
1
Standby mode: HPD[1:3] follows HPD_SINK.  
5:4  
3:2  
Bit 4  
Bit 3  
OVS Control  
0
0
OVS2: DDC sink-side VOL and VIL offset range 2: VIL2 (max): 0.4 V, VOL2 (max): 0.6 V  
0
1
X
OVS3: DDC sink-side VOL and VIL offset range 3: VIL3 (max): 0.3 V, VOL3 (max): 0.5 V  
1
1
OVS1: DDC sink-side VOL and VIL offset range 1: VIL1 (max): 0.4 V, VOL1 (max): 0.7 V  
Output Edge Rate Control  
Fastest edge rate + 90 ps  
Bit 3  
Bit 2  
1
1
1
0
Fastest edge rate + 60 ps  
0
1
Fastest edge rate + 30 ps  
0
Bit 1  
1
0
Bit 0  
0
X
X
Fastest edge rate  
1:0  
Power Mode  
Device enters low-power mode.  
Device enters low-power mode.  
Reserved  
1
1
0
1
0
0
Device is in normal-power mode.  
Copyright © 2008, Texas Instruments Incorporated  
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