TLK10002
SLLSE75 –MAY 2011
www.ti.com
LATENCY_COUNTER_2 — Address: 0x17 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
17.15:12
LATENCY_MEAS_START_COMMA[3:0] Latency measurement start comma location status. “1” indicates
comma found at the start location. If LS TX is selected as start point
(16.7 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS
RX is selected as start point (16.7 = 1), [0] indicates status for
RO/LH(1)
data[9:0], [1] indicates status for data[19:10]. [3:2] is unused.
17.11:8
17.4
LATENCY_MEAS_STOP_COMMA[3:0]
Latency measurement stop comma location status. “1” indicates
comma found at the stop location. If LS RX is selected as stop point
(16.6 = 0), [3:0] indicates status for lane3, lane2, lane1, lane0. If HS
TX is selected as stop point (16.6 = 1), [0] indicates status for
data[9:0], [1] indicates status for data[19:10]. [3:2] is unused.
RO/LH(1)
RO/LH(1)
LATENCY_ MEAS_READY
Latency measurement ready indicator
0 = Indicates latency measurement not complete.
1 = Indicates latency measurement is complete and value in latency
measurement counter (LATENCY_MEAS_COUNT[19:0]) (in registers
17.3:0 and 18.15:0) is ready to be read.
17.3:0
LATENCY_MEAS_COUNT[19:16]
Bits[19:16] of 20 bit wide latency measurement counter.
COR(1)
Latency measurement counter value represents the latency in number
of clock cycles. This counter will return 20’h00000 if it is read before a
comma is received at the stop point. If latency is more than
20’hFFFFF clock cycles then this counter returns 20’hFFFFF.
(1) User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to
20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when
Register 0x18 is read.
LATENCY_COUNTER_1 — Address: 0x18 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
18.15:0
LATENCY_MEAS_COUNT[15:0]
Bits[15:0] of 20 bit wide latency measurement counter.
COR(1)
(1) User has to make sure Register 0x17 has to be read first before reading Register 0x18. Latency measurement counter value resets to
20’h00000 when Register 0x18 is read. Start and Stop Comma (17.15:12 and 17.11:8) and count valid (17.4) bits are also cleared when
Register 0x18 is read.
TI_RESERVED_CONTROL_1 — Address: 0x19 Default: 0x0000
BIT(s)
19.10
19.9
NAME
DESCRIPTION
ACCESS
RW
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
For TI use only. (Default 1’b0)
For TI use only. (Default 1’b0)
For TI use only. (Default 1’b0)
For TI use only. (Default 1’b0)
For TI use only. (Default 2’b00)
For TI use only. (Default 4’b0000)
RW
19.8
RW
19.6
RW
19.5:4
19.3:0
RW
RW
TI_RESERVED_CONTROL_2 — Address: 0x1A Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
1A.15:0
RESERVED
For TI use only.
RW
TI_RESERVED_STATUS_1 — Address: 0x1B Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
1B.15:0
RESERVED
For TI use only.
RO
50
Copyright © 2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
