TLK10002
www.ti.com
SLLSE75 –MAY 2011
MISC_CONTROL_3 — Address: 0x1C Default: 0x3000
BIT(s)
1C.15
1C.14
1C.13
NAME
DESCRIPTION
ACCESS
RW
RESERVED
RESERVED
CLKOUT_B_EN
For TI use only. (Default 1’b0)
For TI use only. (Default 1’b0)
RW
Output clock enable
RW
0 = Holds CLKOUTBP/N output to a fixed value
1 = Allows CLKOUTBP/N output to toggle normally (Default 1'b1)
Output clock enable
1C.12
CLKOUT_A_EN
RW
RW
0 = Holds CLKOUTAP/N output to a fixed value
1 = Allows CLKOUTAP/N output to toggle normally (Default 1'b1)
For TI use only. (Default 10’b0000000000)
1C.9:0
RESERVED
LAS_STATUS_2 — Address: 0x1D Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
RO
1D.15:12
1D.11:8
1D.7:4
LAS_LN3_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 3.
LAS_LN2_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 2.
LAS_LN1_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 1.
LAS_LN0_ALIGN_PTR[3:0] LAS Lane align FIFO character location for lane 0.
RO
RO
1D.3:0
RO
EXT_ADDRESS_CONTROL — Address: 0x1E Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
1E.15:0
EXT_ADDR_CONTROL[15:0] This register should be written with the extended register address to be
RW
written/read. Contents of address written in this register can be accessed from
Register 0x1F. (Default 4’h0000)
EXT_ADDRESS_DATA — Address: 0x1F Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
1F.15:0
EXT_ADDR_DATA[15:0]
This register contains the data associated with the register address written in
Register 0x1E
RO
TI_ RESERVED_STATUS_2 — Address: 0x8000 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
8000.15:0 RESERVED
For TI use only.
RO
TI_RESERVED_STATUS_3 — Address: 0x8001 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
8001.15:0 RESERVED
For TI use only.
RO
TI_RESERVED_STATUS_4 — Address: 0x8002 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
8002.15:0 RESERVED
For TI use only.
RO
TI_RESERVED_STATUS_5 — Address: 0x8003 Default: 0x0000
BIT(s)
NAME
DESCRIPTION
ACCESS
8003.15:0 RESERVED
For TI use only.
RO
Copyright © 2011, Texas Instruments Incorporated
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