TLK10002
www.ti.com
SLLSE75 –MAY 2011
MDC
MDIO
1
PA [4:0]
5'h1E
1
0
1
0
1
0
16'h8000
Data
32 "1's"
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Start
Idle
Preamble
Figure 22. CL22 – Indirect Address Method – Address Write
MDC
1
MDIO
PA [4 :0]
1
0
1
0
1
5'h 1F
0
DATA
Data
32 "1's"
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Start
Idle
Preamble
Figure 23. CL22 - Indirect Address Method – Data Write
The following timing diagrams illustrate an example read transaction to read contents of Register 16’h8000 using
indirect addressing in Clause 22.
MDC
1
MDIO
PA [4:0]
1
0
1
0
1
5'h1E
0
16'h8000
Data
32 "1's"
Write
Code
PHY
Addr
REG
Addr
Turn
Around
Start
Idle
Preamble
Figure 24. CL22 - Indirect Address Method – Address Write
MDC
Pu(1)
0
1
1
0
PA4 PA0
D15
D0
5'h1F
0
1
MDIO
Turn
32 "1's"
Read
Code
PHY
Addr
REG
Addr
Around
Data
Idle
Start
Preamble
(1) Note that the 1 in the Turn Around section is externally pulled up, and driven to Zero by TLK10002.
Figure 25. CL22 - Indirect Address Method – Data Read
The IEEE 802.3 Clause 22 specification defines many of the registers, and additional registers have been
implemented for expanded functionality.
PROGRAMMERS' REFERENCE
The following registers can be addressed directly through MDIO Clause 22. Channel identification is based on
PHY (Port) address field. Channel A can be accessed by setting LSB of PHY address to 0. Channel B can be
accessed by setting LSB of PHY address to 1. Control registers 0x01 through 0x0E are specific to the channel
addressed. Status registers 0x0F through 0x15, and 0x1D report the status of the channel addressed. The rest
are global control/status registers and are channel independent. Please note that the N.x:y register numbering
format is used in this document, where N is a hexadecimal register number, and x:y is a register bit number
range in decimal format. For example, B.10:8 denotes bits 10, 9, and 8 of register address 0x0B.
Copyright © 2011, Texas Instruments Incorporated
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