TLC5970
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SBVS140 –MARCH 2010
Grayscale (GS) First/Second Data Latch (Register Address = 0000b)
The GS Latch is 36 bits long. The second GS Latch controls the pulse width modulation (PWM) for each OUTn.
The first GS Latch holds the data written through the differential signal interface. If the Auto Data Refresh bit in
the Function Control Latch is '1', the data in the first latch are copied to the second latch at the rising edge of the
4096th grayscale clock. If the Auto Data Refresh bit is '0', both the first and second GS Latches are updated at
the same time from the data written into the differential signal interface. When the IC is powered on, both latches
are reset to all '0'. At startup, GS data should not be programmed until after the Function Control Data Latch is
programmed because the PWM control automatically starts when data are written into the second GS Latch.
Table 8 and Figure 26 show the GS Data Latch bit assignments. Table 5 shows an example of OUTn duty cycle
ratios for different GS data.
Table 8. Grayscale Data Latch Bit Assignment
BIT NUMBER
11-0
BIT NAME
GSOUT0
GSOUT1
GSOUT2
DESCRIPTION
Grayscale data for OUT0 (data = 000h to FFFh, default = 000h = LED off)
Grayscale data for OUT1 (data = 000h to FFFh, default = 000h = LED off)
Grayscale data for OUT2 (data = 000h to FFFh, default = 000h = LED off)
23-12
35-24
Grayscale First Data Latch
MSB
35
LSB
0
34
25
OUT2
24
23
22
13
12
11
10
1
OUT2 OUT2
GS Data GS Data
OUT2
OUT1
OUT1
OUT1
OUT1
OUT0
GS Data GS Data GS Data GS Data GS Data GS Data
OUT0
OUT0
OUT0
¼
¼
¼
GS Data GS Data GS Data GS Data
Bit 1
Bit 11
Bit 10
Bit 0
Bit 11
Bit 10
Bit 1
Bit 0
Bit 11
Bit 10
Bit 1
Bit 0
MSB
35
LSB
0
34
25
24
23
22
13
12
11
10
1
OUT2
OUT2
OUT2
OUT2
OUT1
OUT1
OUT1
OUT1
OUT0
OUT0
OUT0
OUT0
¼
¼
¼
GS Data GS Data
Bit 11 Bit 10
GS Data GS Data GS Data GS Data
Bit 1 Bit 0 Bit 11 Bit 10
GS Data GS Data GS Data GS Data
Bit 1 Bit 0 Bit 11 Bit 10
GS Data GS Data
Bit 1 Bit 0
Grayscale Second Data Latch
36
To Display Timing Control Block
Figure 26. GS Data Latch Bit Assignment
Function Control (FC) and Global Brightness Control (BC) First/Second Data Latch
(Register Address = 1111b)
The FC and BC first Data Latch total bit length is 15 bits. The BC second latch bit length is seven bits. The FC
data are used to set the function mode; the BC second data latch sets the current ratio of each constant-current
output. The BC first latch holds the data written through the differential signal interface, and the latched data in
the first latch are copied to the second latch at the rising edge of the 4096th GS clock when the auto data refresh
bit is set to '1' in the FC latch. The first and second latch data are updated at the same time by the data written
through the differential signal interface when the auto data refresh bit is set to '0'. When the IC is powered on,
the FC data should be set before the GS data setting because the PWM control starts as soon as the GS data
(except '0') are written into this second latch.
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