TLC5970
SBVS140 –MARCH 2010
www.ti.com
35
34
33
2
1
0
40-Bit Common Shift Register (Default = 0h)
Latch Address Bits (4 Bits)
MSB
Latch Data (36 Bits)
LSB
0
39
38
37
36
35
34
33
2
1
SIN
Shift in data from the
differential signal receiver.
Latch
Latch
Latch
Latch
Latch
Data
Bit 35
Latch
Data
Bit 34
Latch
Data
Bit 33
Latch
Data
Bit 2
Latch
Data
Bit 1
Latch
Data
Bit 0
SOUT
Shift out data to the
differential line driver.
¼
Address Address Address Address
Bit 3 Bit 2 Bit 1 Bit 0
SCLK
Shift clock from the
differential signal receiver.
35
34
33
2
1
0
Latch pulse from the
pulse generator
4
(the latch pulse is generated
after the programmed time
set by the data in the function
control data latch from the
last shift clock when the
auto refresh bit is ‘1’).
MSB
35
LSB
0
34
33
2
1
Latch Address
4-Bit Decoder
OUT2
GS
Bit 11
OUT2
GS
Bit 10
OUT2
GS
Bit 9
OUT0
GS
Bit 2
OUT0
GS
Bit 1
OUT0
GS
Bit 0
Address = 0000b
¼
Grayscale First Data Latch (Default = 0)
MSB
35
LSB
0
34
33
2
1
Address = 1001b
OUT2
GS
Bit 11
OUT2
GS
Bit 10
OUT2
GS
Bit 9
OUT0
GS
Bit 2
OUT0
GS
Bit 1
OUT0
GS
Bit 0
Restart Operation
From OVP/SCP Error
¼
36
Grayscale Second Data Latch (Default = 0)
MSB
35
LSB
0
34
TI
33
TI
2
1
Address = 1010b
TI
Over
Short-
Circuit
Protection Protection Detection
LED
¼
Reserved Reserved Reserved
Bit 30 Bit 29 Bit 28
Voltage
Open
Status Information Data (SID) Read Out Register
35
35
34
34
33
33
2
2
1
1
0
0
MSB
35
LSB
0
34
33
2
1
Latch
Delay
Time
Bit 3
Latch
Delay
Time
Bit 2
OUT0
DC
Bit 2
OUT0
DC
Bit 1
OUT0
DC
Bit 0
Address = 1011b
TI
¼
Reserved
Bit 0
EEPROM Data Read Out Register
35
35
34
34
33
33
2
2
1
1
0
0
36
MSB
35
LSB
0
34
Write
33
Write
2
1
PH
PH
PH
Address = 1100b
Write
¼
Command Command Command
Bit 7 Bit 6 Bit 5
On-Duty On-Duty On-Duty
Bit 2 Bit 1 Bit 0
36
EEPROM1 Write Data Latch
36-Bit
EEPROM
35
36
14
35
34
33
2
1
0
MSB
35
LSB
0
34
33
Write
2
1
21
OUT2
DC
Bit 2
OUT2
DC
Bit 1
OUT2
DC
Bit 0
Address = 1101b
Lower 31
Write
Write
¼
Lower 20
Command Command Command
Bit 7 Bit 6 Bit 5
EEPROM2 Write Data Latch
20
19
2
1
0
MSB
20
LSB
0
19
2
1
OUT2
DC
Bit 6
OUT2
DC
Bit 5
OUT0
DC
Bit 2
OUT0
DC
Bit 1
OUT0
DC
Bit 0
Address = 1110b
¼
Lower 12
Dot Correction Data Latch (Default = Data in EEPROM2)
11
MSB
6
0
LSB
11
6
0
DC Data
Load
Control
Address = 1111b
Brightness
Bit 6
Brightness
¼
Bit 0
¼
Function Control Data Latch
(Default = 007Fh)
MSB
6
LSB
0
Latch pulse from the display timing control block.
(This latch pulse is generated at the end of one display
period or the timing of the display timing reset when the
auto refresh bit is ‘1’. Also, when the auto refresh
bit is ‘0’, the latch pulse is generated when the grayscale
or global brightness control data are written.
Global Brightness Control
Second Data Latch
(Default = 7Fh)
Brightness
Bit 6
Brightness
Bit 0
¼
8
4
2
To Buck To Latch Pulse To Differential
Signal Interface
Block
Converter
Block
Generator
Block
Figure 25. Register and Data Latch Configuration
32
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TLC5970
TI [ TEXAS INSTRUMENTS ]
