TLC5970
SBVS140 –MARCH 2010
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SDTA
SDTB
SCKA
SCKB
The latch pulse is generated after the programmed time
from the last shift clock rising edge.
1
2
3
Generated Shift Clock
(Internal)
Generated Shift Register
(Internal)
The GS first latch data are copied to the second latch at the 4096th rising edge of
the reference clock when auto-repeat mode is on and while in no GS counter reset mode.
Generated Latch Pulse
(Internal)
GS First Latch
(Internal)
GS Second Latch
(Internal)
4096
1
2
1022 1023 1024 1025 1026 1027 4095 4096
1
2
3
4094 4095 4096
1
2
3
4
1/2 Divided Internal Oscillator Clock
(Internal)
Grayscale Counter
(Internal)
FFF 000 001
3FE 3FF 400 401 402
FFF 000 001 002
FFE FFF 000 001 001 002
1
0
Function Control Bit 13
(External Grayscale Clock)
1
0
Function Control Bit 14
(Display Timing Reset)
No drivers turn on when the grayscale data are '0'.
OFF
ON
OUTn
(GSDATA = 000h)
OUTn is not turned on again until the next latch pulse input when
auto repeat is off (AutoRpt bit of the function control latch = 0).
T = Internal OSC Clock ´ 1
OFF
ON
OUTn
(GSDATA = 001h)
OUTn is not turned on again for auto repeat on mode
(AutoRpt bit of the function control latch = 1)
T = Internal OSC Clock ´ 2
OFF
ON
OUTn
(GSDATA = 002h)
T = Internal OSC Clock ´ 1023
OFF
ON
OUTn
(GSDATA = 3FFh)
T = Internal OSC Clock ´ 1024
T = Internal OSC Clock ´ 1025
OFF
ON
OUTn
(GSDATA = 400h)
OFF
ON
OUTn
(GSDATA = 401h)
T = Internal OSC Clock ´ 4094
OFF
ON
OUTn
(GSDATA = FFEh)
T = Internal OSC Clock ´ 4095
OFF
ON
OUTn
(GSDATA = FFFh)
Figure 24. PWM Operation (Internal GS Clock Mode)
30
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