TLC5970
www.ti.com
SBVS140 –MARCH 2010
SDTA
SDTB
SCKA
SCKB
The latch pulse is generated after
the programmed time from the
last serial clock rising edge.
Pre-Boost Period
17
1
2
18
1040 1041
4111 4112
1
2
Generated Shift Clock
(Internal)
Generated Shift Register Data
(Internal)
The GS first and second latches are updated at the same time when the latch pulse
is generated with the display timing reset mode enabled.
Generated Latch Pulse
(Internal)
GS First Latch Data
(Internal)
GS Second Latch Data
(Internal)
1/2 Divided Internal Oscillator Clock
(Internal)
Grayscale Counter
(Internal)
XXX FF0
FF1
001
002
400
401 FFE FFF
000
001
002
1
0
Function Control Bit 13
(External GS clock)
1
0
Function Control Bit 14
(Display Timing Reset)
GS counter is set to FF0h when the latch pulse is generated for
GS data when the display timing reset bit is '1'.
OFF
ON
OUTn
(GSDATA = 000h)
No drivers turn on when
grayscale data are '0'.
OUTn is not turned on again until the next latch pulse is input for
auto repeat off mode (AutoRpt bit of the function control latch = 0).
T = Shift Clock ´ 1
OFF
ON
OUTn
(GSDATA = 001h)
OUTn is turned on again for auto repeat on mode
(AutoRpt bit of the function control latch = 1).
OFF
ON
OUTn
(GSDATA = 002h)
T = Shift Clock ´ 1023
OFF
ON
OUTn
(GSDATA = 3FFh)
T = Shift Clock ´ 1024
OFF
ON
OUTn
(GSDATA = 400h)
OFF
ON
OUTn
(GSDATA = 401h)
OFF
ON
T = Shift Clock ´ 4094
OUTn
(GSDATA = FFEh)
OFF
ON
T = Shift Clock ´ 4095
OUTn
(GSDATA = FFFh)
Figure 23. PWM Operation (External GS Clock Mode)
Copyright © 2010, Texas Instruments Incorporated
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