TLC5970
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SBVS140 –MARCH 2010
FB Target Voltage
These bits select the target voltage of the FB pin. The FB pin is connected to the LED anode side. The set data
should be determined by Equation 12. Also, the set data should be set to the higher voltage of the three-color
LED line. The buck converter chargeup FB voltage to the FB target voltage (VFB) is set by these bits with a
soft-start sequence after the IC is powered on.
VFB (V) = Typical LED forward voltage × the number of LED in series + 1 V.
VFB set data can be calculated by Equation 12:
(VFB - 7) ´ 31
FB Set Data for VFB =
10
(12)
(13)
FB voltage (VFB) can be calculated by Equation 13:
10 ´ FB Set Data
FB Voltage (V) =
+ 7
31
Table 13 lists the FB voltage set by FB set data.
Table 13. FB Target Voltage Selection Truth Table
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
TARGET FB
VOLTAGE (V)
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
TARGET FB
VOLTAGE (V)
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
0
1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
7.0
7.3
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
12.2
12.5
2
7.6
12.8
3
8.0
13.1
4
8.3
13.5
5
8.6
13.8
6
8.9
14.1
7
9.3
14.4
8
9.6
14.7
9
9.9
15.1
10
11
12
13
14
15
10.2
10.5
10.9
11.2
11.5
11.8
15.4
15.7
16.0
16.4
16.7
17.0
Differential Signal Interface (DSI) Timing Mode
These bits select a differential interface timing mode from three types of timing modes, as shown in Table 14.
Table 14. DSI Timing Mode Selection Truth Table
DSIMOD DATA (Binary)
DSIMOD DATA (Decimal)
DSIMOD DATA (Hex)
SELECTED MODE
Mode 0 (factory default)
Mode 1
00
01
10
11
0
1
2
3
0
1
2
3
Mode 2
Mode 2
Mode 0 is a low-frequency transfer mode. Maximum transfer frequency is lowest in the timing modes but it is
easy to transfer the data over long distances without transmission errors because this mode can control the data
hold time for the next connected device. The SCKY/SCKZ output level is controlled by the SCKA/SCKB level.
SCKY/SCKZ go to a high level when the SCKA/SCKB level is high. The SCKY/SCKZ output level is controlled by
the SCKA/SCKB level. SCKY/SCKZ go to a low level when the SCKA/SCKB level is low. The SDTY/SDTZ data
change after 30 ns (typical) from when the SCKA/SCKB falling clock is input.
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