ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map (continued)
808000h
808004h
808006h
808008h
808020h
808024h
808028h
808030h
808034h
808038h
808040h
DMA Global Control
DMA Source Address
DMA Destination Address
DMA Transfer Counter
Timer 0 Global Control
Timer 0 Counter
Timer 0 Period
Timer 1 Global Control
Timer 1 Counter
Timer 1 Period Register
Serial Port 0 Global Control
808042h
808043h
808044h
808045h
808046h
FSX/DX/CLKX Serial Port 0 Control
FSR/DR/CLKR Serial Port 0 Control
Serial Port 0 R/X Timer Control
Serial Port 0 R/X Timer Counter
Serial Port 0 R/X Timer Period
808048h
80804Ch
808050h
Serial Port 0 Data Transmit
Serial Port 0 Data Receive
Serial Port 1 Global Control
808052h
808053h
808054h
808055h
808056h
FSX/DX/CLKX Serial Port 1 Control
FSR/DR/CLKR Serial Port 1 Control
Serial Port 1 R/X Timer Control
Serial Port 1 R/X Timer Counter
Serial Port 1 R/X Timer Period
808058h
80805Ch
808060h
808064h
Serial Port 1 Data Transmit
Serial Port 1 Data Receive
Expansion-Bus Control
Primary-Bus Control
†
Shading denotes reserved address locations
†
Figure 3. Peripheral Bus Memory-Mapped Registers
6
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