ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
functional block diagram
RAM
RAM
ROM
Cache
(64 × 32)
Block 0
Block 1
Block
(1K × 32)
(1K × 32)
(4K × 32)
32
24
24
32
24
32
24
32
PDATA Bus
PADDR Bus
XRDY
RDY
HOLD
MSTRB
IOSTRB
XR /W
DDATA Bus
HOLDA
STRB
DADDR1 Bus
XD31−XD0
XA12 −XA0
R / W
DADDR2 Bus
D31−D0
A23 −A0
DMADATA Bus
DMAADDR Bus
32
24
32
24
24
32
24
DMA Controller
Serial Port 0
Serial-Port-Control
FSX0
Global-Control
Register
Register
DX0
MUX
CLKX0
FSR0
DR0
Receive/Transmit
IR
(R/X) Timer Register
Source-Address
Register
PC
CPU1
CPU2
REG1
REG2
RESET
INT(3 −0)
IACK
Data-Transmit
Register
CLKR0
Destination-
Address
Register
Data-Receive
Register
MC /MP
XF(1,0)
Transfer-
Counter
Register
V
DD
Serial Port 1
IODV
32
32
40
40
DD
Serial-Port-Control
Register
ADV
DD
FSX1
DX1
32-Bit
Barrel
Shifter
PDV
DD
Multiplier
DDV
DD
CLKX1
FSR1
DR1
Receive/Transmit
(R/X) Timer Register
MDV
DD
ALU
40
40
V
SS
Data-Transmit
Register
DV
CLKR1
SS
40
40
CV
SS
IV
SS
40
Extended-
Precision
Registers
(R7−R0)
40
32
Data-Receive
Register
V
BBP
V
SUBS
X1
Timer 0
X2 /CLKIN
H1
Global-Control
Register
DISP0, IR0, IR1
H3
TCLK0
Timer-Period
Register
ARAU0
ARAU1
EMU(6 −0)
RSV(10 −0)
BK
Timer-Counter
Register
24
24
24
24
Auxiliary
Registers
(AR0 −AR7)
Timer 1
32
32
Global-Control
Register
32
32
TCLK1
Timer-Period
Register
32
32
Other
Registers
(12)
Timer-Counter
Register
Port Control
Primary-Control
Register
Expansion-Control
Register
3
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TI [ TEXAS INSTRUMENTS ]
