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SM320C30GBM40 参数 Datasheet PDF下载

SM320C30GBM40图片预览
型号: SM320C30GBM40
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [DIGITAL SIGNAL PROCESSOR]
分类和应用: 外围集成电路数字信号处理器时钟
文件页数/大小: 47 页 / 721 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号SM320C30GBM40的Datasheet PDF文件第4页浏览型号SM320C30GBM40的Datasheet PDF文件第5页浏览型号SM320C30GBM40的Datasheet PDF文件第6页浏览型号SM320C30GBM40的Datasheet PDF文件第7页浏览型号SM320C30GBM40的Datasheet PDF文件第9页浏览型号SM320C30GBM40的Datasheet PDF文件第10页浏览型号SM320C30GBM40的Datasheet PDF文件第11页浏览型号SM320C30GBM40的Datasheet PDF文件第12页  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ  
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ  
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004  
Pin Functions (Continued)  
CONDITIONS  
WHEN  
SIGNAL IS Z TYPE  
PIN  
DESCRIPTION  
TYPE  
QTY  
NAME  
§
SERIAL PORT 0 SIGNALS  
Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0  
transmitter.  
CLKX0  
DX0  
1
1
1
I/O/Z  
S
S
S
R
R
R
I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0.  
Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data  
process over DX0.  
FSX0  
I/O/Z  
CLKR0  
DR0  
1
1
I/O/Z Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver.  
I/O/Z Data receive. Serial port 0 receives serial data on DR0.  
S
S
R
R
Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data  
process over DR0.  
FSR0  
1
I/O/Z  
S
R
SERIAL PORT 1 SIGNALS  
Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1  
transmitter.  
CLKX1  
DX1  
1
1
1
I/O/Z  
S
S
S
R
R
R
I/O/Z Data transmit output. Serial port 1 transmits serial data on DX1.  
Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data  
process over DX1.  
FSX1  
I/O/Z  
CLKR1  
DR1  
1
1
I/O/Z Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver.  
I/O/Z Data receive. Serial port 1 receives serial data on DR1.  
S
S
R
R
Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data  
process over DR1.  
FSR1  
1
1
1
I/O/Z  
S
S
S
R
R
R
TIMER 0 SIGNALS  
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an  
output, TCLK0 outputs pulses generated by timer 0.  
TCLK0  
TCLK1  
I/O/Z  
TIMER 1 SIGNALS  
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an  
output, TCLK1 outputs pulses generated by timer 1.  
I/O/Z  
SUPPLY AND OSCILLATOR SIGNALS (see Note 1)  
V
4
2
2
1
2
1
4
4
2
I
I
I
I
I
I
I
I
I
5-V supply  
5-V supply  
5-V supply  
5-V supply  
5-V supply  
5-V supply  
Ground  
DD  
IODV  
DD  
ADV  
PDV  
DDV  
DD  
DD  
DD  
MDV  
DD  
V
SS  
DV  
CV  
Ground  
SS  
SS  
Ground  
§
I = input, O = output, Z = high-impedance state, NC = no connect  
For GB package  
S = SHZ active, H = HOLD active, R = RESET active  
Recommended decoupling capacitor is 0.1 µF.  
NOTE 1: CV , V , and IV  
are on the same plane.  
SS SS  
SS  
8
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
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