ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map (continued)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
Reset
INT0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
1Fh
20h
Reset
INT0
INT1
INT1
INT2
INT2
INT3
INT3
XINT0
RINT0
XINT1
RINT1
TINT0
TINT1
DINT
XINT0
RINT0
XINT1
RINT1
TINT0
TINT1
DINT
Reserved
TRAP 0
Reserved
TRAP 0
1Fh
20h
.
.
.
.
.
.
3Bh
3Ch
3Fh
TRAP 27
3Bh
3Ch
BFh
TRAP 27
Reserved
Reserved
(a) Microprocessor Mode
(a) Microcomputer Mode
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
5
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