ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
description (continued)
196-Pin HFG Quad Flatpack
(TOP VIEW)
181-Pin GB Grid Array Package
(BOTTOM VIEW)
A B C D E F G H J K L M N P R
1
2
3
4
1
147
5
DVDD DVSS
6
7
8
9
10
11
12
13
14
15
DVSS DVDD
49
99
The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced by the large address space, multiprocessor interface, internally
and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple
interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to
dedicated coprocessor.
High-level language support is implemented easily through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
For additional information when designing for cold temperature operation, please see Texas Instruments
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature
number SGUA001.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
