ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢅ
ꢇ ꢈꢉ ꢈꢊꢋ ꢌ ꢀꢈ ꢉꢍ ꢋ ꢌ ꢎ ꢏꢐ ꢆꢑ ꢀꢀ ꢐꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
memory map
Figure 1 shows the memory map for the SMJ320C30. See the TMS320C3x User’s Guide (literature number
SPRU031) for a detailed description of this memory mapping. Figure 2 shows the reset, interrupt, and trap
vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers.
0h
0h
Reset, Interrupt, Trap
Vectors, and Reserved
Locations (64) (External
STRB Active)
Reset, Interrupt,
Trap Vectors, and Reserved
Locations (192)
0BFh
0C0h
03Fh
040h
ROM
(Internal)
0FFFh
1000h
External
STRB Active
External
STRB Active
(8M Words − 64 Words)
(8M Words − 4K Words)
7FFFFFh
800000h
7FFFFFh
800000h
Expansion-Bus
MSTRB Active
(8K Words)
Expansion-Bus
MSTRB Active
(8K Words)
801FFFh
802000h
801FFFh
802000h
Reserved
Reserved
(8K Words)
(8K Words)
803FFFh
804000h
803FFFh
804000h
Expansion-Bus
IOSTRB Active
(8K Words)
Expansion-Bus
IOSTRB Active
(8K Words)
805FFFh
806000h
805FFFh
806000h
Reserved
Reserved
(8K Words)
(8K Words)
807FFFh
808000h
807FFFh
808000h
Peripheral-Bus
Memory-Mapped
Registers
Peripheral-Bus
Memory-Mapped
Registers
(6K Words Internal)
(6K Words Internal)
8097FFh
809800h
8097FFh
809800h
RAM Block 0
RAM Block 0
(1K Word Internal)
(1K Word Internal)
809BFFh
809C00h
809BFFh
809C00h
RAM Block 1
RAM Block 1
(1K Word Internal)
(1K Word Internal)
809FFFh
80A000h
809FFFh
80A000h
External
STRB Active
(8M Words − 40K Words)
External
STRB Active
(8M Words − 40K Words)
0FFFFFFh
0FFFFFFh
(a) Microprocessor Mode
(b) Microcomputer Mode
Figure 1. Memory Map
4
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