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ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
pin functions
This section gives signal descriptions for the SMJ320C30 devices in the microprocessor mode. The following
tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance
state as indicated by I, O, or Z, respectively), and a brief function description. All pins labeled NC have special
functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates
that the signal is active low (true at logic-0 level). The signals are grouped according to functions.
Pin Functions
CONDITIONS
WHEN
SIGNAL IS Z TYPE
PIN
†
DESCRIPTION
TYPE
‡
QTY
NAME
§
PRIMARY BUS INTERFACE
D31−D0
A23−A0
32
24
I/O/Z 32-bit data port of the primary bus interface
S
S
H
H
O/Z
O/Z
O/Z
I
24-bit address port of the primary bus interface
R
R
Read/write for primary bus interface. R/W is high when a read is performed and low
when a write is performed over the parallel interface.
R/W
STRB
RDY
1
1
1
S
S
H
H
External access strobe for the primary bus interface
Ready. RDY indicates that the external device is prepared for a primary bus interface
transaction to complete.
Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction
is completed. A23−A0, D31−D0, STRB, and R/W are in the high-impedance state
and all transactions over the primary bus interface are held until HOLD becomes a
logic high or the NOHOLD bit of the primary bus control register is set.
HOLD
1
1
I
Hold acknowledge for primary bus interface. HOLDA is generated in response to a
logic low on HOLD. HOLDA indicates that A23−A0, D31−D0, STRB, and R/W are
in the high-impedance state and that all transactions over the bus are held. HOLDA
is high in response to a logic high of HOLD or when the NOHOLD bit of the primary
bus control register is set.
HOLDA
O/Z
S
EXPANSION BUS INTERFACE
XD31−XD0
XA12−XA0
32
13
I/O/Z 32-bit data port of the expansion bus interface
S
S
R
R
O/Z
13-bit address port of the expansion bus interface
Read/write signal for expansion bus interface. When a read is performed, XR/W is
held high; when a write is performed, XR/W is low.
XR/W
1
O/Z
S
R
MSTRB
IOSTRB
1
1
O/Z
O/Z
External memory access strobe for the expansion bus interface
External I/O access strobe for the expansion bus interface
S
S
Ready signal. XRDY indicates that the external device is prepared for an expansion
bus interface transaction to complete.
XRDY
1
I
CONTROL SIGNALS
Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
RESET
1
4
1
1
2
I
INT3−INT0
IACK
I
External interrupts
Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. IACK can
be used to indicate the beginning or end of an interrupt-service routine.
O/Z
I
S
S
MC/MP
XF1, XF0
Microcomputer/microprocessor mode
External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instructions.
I/O/Z
R
†
‡
§
I = input, O = output, Z = high-impedance state, NC = no connect
For GB package
S = SHZ active, H = HOLD active, R = RESET active
7
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