ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and the reverse.
timing parameters for peripheral pin changing from general-purpose output to input mode
(see Note 12 and Figure 27)
320C30-40
320C30-50
†
NO.
UNIT
MIN
MAX
MIN
MAX
95
96
97
t
t
t
Hold time after H1 high
13
10
ns
ns
ns
h(H1H)
Setup time, peripheral pin before H1 low
Hold time, peripheral pin after H1 low
9
0
9
0
su(GPIOH1L)
h(GPIOH1L)
†
Numbers in this column are used in Figure 27.
NOTE 12: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined
by the contents of internal control registers associated with each peripheral.
Execute Store
of Peripheral
Control
Value on
Terminal Seen in
Peripheral
Buffers Go
From Output to
Input
Synchronizer Delay
Register
Control Register
H3
H1
96
I/O
Control Bit
97
95
Peripheral
Pin
Output
Data Bit
Data Sampled
Data
Seen
Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
37
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