RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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4.7.3.2 Mapping of DCC Clock Source Inputs
Table 4-16. DCC1 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
oscillator (OSCIN)
high frequency LPO
test clock (TCK)
others
0x5
0xA
Table 4-17. DCC1 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
others
-
0x0
N2HET1[31]
Main PLL free-running clock output
PLL #2 free-running clock output
low frequency LPO
high frequency LPO
reserved
0x1
0x2
0xA
0x3
0x4
0x5
EXTCLKIN1
0x6
EXTCLKIN2
0x7
reserved
0x8 - 0xF
VCLK
Table 4-18. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
others
0xA
oscillator (OSCIN)
test clock (TCK)
Table 4-19. DCC2 Counter 1 Clock Sources
KEY [3:0]
others
0xA
CLOCK SOURCE [3:0]
CLOCK NAME
N2HET2[0]
Reserved
VCLK
-
00x0 - 0x7
0x8 - 0xF
72
System Information and Electrical Specifications
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