RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
www.ti.com
4.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in the figures below.
GCM
0
GCLK, GCLK2 (to CPU)
HCLK (to SYSTEM)
OSCIN
PLL #1 (FMzPLL)
1
X1..256
/1..32
/1..64
/1..8
*
/1..16
VCLK_peri (VCLK to peripherals on PCR1)
VCLK_sys (VCLK to system modules)
VCLK2 (to N2HETx and HTUx)
4
5
80kHz
/1..16
/1..16
Low Power
Oscillator
10MHz
VCLK3 (to Ethernet, USB)
PLL # 2 (FMzPLL)
0
1
3
6
/1..32
*
/1..64 X1..256
/1..8
4
5
6
VCLKA1 (to DCANx)
VCLKA3_S (left open)
3
7
EXTCLKIN1
EXTCLKIN2
* the frequency at this node must not
exceed the maximum HCLK specifiation.
7
VCLK
0
1
3
4
5
6
VCLKA3_DIVR / 4
VCLKA3_DIVR
7
VCLK
VCLK3
/DIVR
VCLKA3_DIVR
(to USB Device / 48MHZ
and USB Host / 48 MHz)
VCLKA4_DIVR
VCLKA3_DIVR / 4
(to USB Host / 12 MHz)
/4
0
1
3
4
5
6
7
VCLKA4_S (left open)
VCLKA4_SRC
Ethernet
USB Host
VCLK
VCLKA4_DIVR
VCLKA3_DIVR
/DIVR
VCLKA4_DIVR_EMAC
(to EMAC)
PLL2 ODCLK/8
PLL2 ODCLK/16
/1, 2, 4, or 8
0
1
3
4
5
6
7
RTICLK (to RTI, DWWD)
EMIF
USB Device
VCLK
VCLK
VCLKA1
VCLK2
VCLK2
HRP
/1..64
/1,2,..256
/2,3..224
/1,2..32
/1,2..65536
/1,2..256
/1,2,..1024
N2HETx
TU
LRP
/20..25
Prop_seg
Phase_seg2
I2C baud
rate
ECLK
SPI
Baud Rate
ADCLK
LIN / SCI
Baud Rate
Phase_seg1
I2C
Loop
High
Resolution Clock
SPIx,MibSPIx
LIN, SCI
External Clock
MibADCx
EXTCLKIN1
NTU[3]
NTU[2]
NTU[1]
NTU[0]
CAN Baud Rate
DCANx
PLL#2 output
Reserved
N2HETx
RTI
Reserved
Figure 4-7. Device Clock Domains
68
System Information and Electrical Specifications
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