RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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4.6.3 Clock Test Mode
The RM4x platform architecture defines a special mode that allows various clock signals to be brought out
on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very
useful for debugging purposes and can be configured via the CLKTEST register in the system module.
Table 4-15. Clock Test Mode Options
SEL_ECP_PIN
SEL_GIO_PIN
=
=
SIGNAL ON ECLK
SIGNAL ON N2HET1[12]
CLKTEST[3-0]
CLKTEST[11-8]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Oscillator Valid Status
Main PLL Valid status
Reserved
Main PLL free-running clock output
Reserved
EXTCLKIN1
Reserved
LFLPO
Reserved
HFLPO
HFLPO Valid status
Secondary PLL Valid Status
Reserved
Secondary PLL free-running clock output
EXTCLKIN2
GCLK
LFLPO
RTI Base
Oscillator Valid status
Oscillator Valid status
Oscillator Valid status
Oscillator Valid status
VCLKA3_S
Reserved
VCLKA1
Reserved
VCLKA3_DIVR
VCLKA4_DIVR
Reserved
VCLKA4_S
Oscillator Valid status
70
System Information and Electrical Specifications
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