RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
4.6.1.3 Phase Locked Loop (PLL) Clock Modules
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
•
Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The
frequency modulation capability of PLL2 is permanently disabled.
•
•
•
Configurable frequency multipliers and dividers.
Built-in PLL Slip monitoring circuit.
Option to reset the device on a PLL slip detection.
4.6.1.3.1 Block Diagram
Figure 4-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and
PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the
multiplier and dividers for PLL2.
/NR
/OD
/R
PLLCLK
OSCIN
INTCLK
VCOCLK
post_ODCLK
PLL
/1 to /64
/1 to /8
/1 to /32
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
/NF
/1 to /256
/NR2
/OD2
/R2
PLL2CLK
OSCIN
VCOCLK2
INTCLK2
post_ODCLK2
/1 to /64
PLL#2
/1 to /8
/1 to /32
fPLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2)
/NF2
/1 to /256
Figure 4-6. PLLx Block Diagram
4.6.1.3.2 PLL Timing Specifications
Table 4-11. PLL Timing Specifications
PARAMETER
MIN
MAX
f(OSC_SQR)
400
UNIT
fINTCLK
PLL1 Reference Clock frequency
1
MHz
MHz
fpost_ODCLK
Post-ODCLK – PLL1 Post-divider input
clock frequency
fVCOCLK
VCOCLK – PLL1 Output Divider (OD) input
clock frequency
150
1
550
MHz
fINTCLK2
PLL2 Reference Clock frequency
f(OSC_SQR)
400
MHz
MHz
fpost_ODCLK2
Post-ODCLK – PLL2 Post-divider input
clock frequency
fVCOCLK2
VCOCLK – PLL2 Output Divider (OD) input
clock frequency
150
550
MHz
Copyright © 2012, Texas Instruments Incorporated
System Information and Electrical Specifications
65
Submit Documentation Feedback
Product Folder Links: RM46L450 RM46L850
TI [ TEXAS INSTRUMENTS ]
