RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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5.2 Enhanced Capture Modules (eCAP)
Figure 5-3 shows how the eCAP modules are interconnected on this microcontroller.
EPWM1SYNCO
ECAP1SYNCI
ECAP1
ECAP1INTn
ECAP1
VIM
VBus32
VCLK4, SYS_nRST
ECAP1ENCLK
ECAP1SYNCO
ECAP2SYNCI
ECAP2
ECAP
ECAP2INTn
VIM
2/3/4/5
VBus32
VCLK4, SYS_nRST
ECAP2ENCLK
ECAP2SYNCO
ECAP6
ECAP
6
VBus32
VIM
ECAP6INTn
VCLK4, SYS_nRST
ECAP6ENCLK
Figure 5-3. eCAP Module Connections
5.2.1 Clock Enable Control for eCAPx Modules
Each of the ECAPx modules have a clock enable (ECAPxENCLK). These signals need to be generated
from a device-level control register. When SYS_nRST is active low, the clock enables are ignored and the
ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the
state of clock enable is respected.
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Peripheral Information and Electrical Specifications
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