PGA400-Q1
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SLDS186 –MARCH 2012
5.11 Serial Peripheral Interface (SPI) Interface
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0.7 × VDD
–0.3
TYP
MAX
UNIT
V
VIH
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
SPI Frequency
VDD + 0.3
0.3 × VDD
VIL
V
VOH
VOL
fSCK
tCSSCK
4.0
V
0.8
4
V
MHz
ns
CS Low to First SCK Rising Edge
25
Last SCK Rising Edge to CS Rising
Edge
tSCKCS
125
ns
tCSD
CS Disable Time
SDI Setup Time
500
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
tDH
SDI Hold Time
25
tSDIS
tSCKR
tSCKF
tSCKH
tSCKL
tSDOE
tACCS
tSDOD
tSDOS
SDI Fall/Rise Time
SCK Rise Time
7
7
7
SCK Fall Time
SCK High Time
125
125
15
SCK Low Time
SDO Enable Time
SCK Rising Edge to SDO Data Valid
SDO Disable Time
SDO Rise/Fall Time
15
15
11
3
Capacitive Load for Data Output
(SDO)
CL(SDO)
10
pF
Figure 5-1. SPI Timing
Copyright © 2012, Texas Instruments Incorporated
ELECTRICAL CHARACTERISTICS
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