PGA400-Q1
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SLDS186 –MARCH 2012
5.14 GPIO
PARAMETER
TEST CONDITIONS
LOAD ≥ 10 kΩ to VDD or to 0 V
LOAD ≥ 10 kΩ to VDD or to 0 V
MIN
0.7 × VDD
–0.3
TYP
MAX
VDD + 0.3
0.3 × VDD
UNIT
V
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
Pull-up resistance
R
R
V
VOH
VOL
IOH
IOL
IOH = 1 mA
IOL = –1 mA
VOH = 4.5 V
VOL = 0.5 V
4.0
V
0.8
1
V
mA
mA
kΩ
1
RPU
160
5.15 DAC1 and DAC2 Output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC Code 000h to FFFh
Settling time
step.Output is 90% of Full Scale.
RLOAD = 5 kΩ, CLOAD = 500 pF
7
µs
Zero scale error
Full scale voltage
DAC code = 000h, IDAC = 1.5 mA
46
mV
V
Output when DAC code is FFFh,
IDAC = - 1.5 mA
4.85
4.95
DAC Code = 0FFFh , DAC Code =
0000h
Output current amplitude
1.5
mA
Short circuit source current
Short circuit sink current
INL (best-fit line)
VDD = 5V, DAC code = 000h
VDD = 5V, DAC code = FFFh
-34
10
-10
34
mA
mA
-3.5
3.5
LSB
5.16 Input Capture and Output Compare
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CAPTURE PORTS
VIH
VIL
High-level input voltage
Low-level input voltage
R
LOAD ≥ 10 kΩ to VDD or to 0 V
LOAD ≥ 10 kΩ to VDD or to 0 V
0.7 × VDD
–0.3
VDD + 0.3
0.3 × VDD
V
V
R
10_20_MHZ bit = 1
10_20_MHZ bit = 0
10
20
16
Input capture timer clock frequency
Input capture timer bits
MHz
Bits
OUTPUT COMPARE PORTS
VOH
VOL
High-level output voltage
IOH = 1 mA
VDD – 1.0
V
V
Low-level output voltage
IOL = -1 mA
0.8
10_20_MHZ bit = 1
10_20_MHZ bit = 0
10
20
16
Output compare timer frequency
MHz
Output compare timer bits
High-level output current
Low-level output current
Bits
mA
mA
IOH
IOL
1
1
Copyright © 2012, Texas Instruments Incorporated
ELECTRICAL CHARACTERISTICS
11
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