ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
a digital output pin intended to
www.ti.com
External Clock
SYNCOUT
Figure 45 shows the external clock connection. The
clock is applied to XTAL1/CLKIN and XTAL2 floats.
Make sure a clean clock input is applied to the
ADS1259, free of overshoot and glitches. A series
resistor often helps to reduce overshoot and should
be placed close to the driving end of the clock
source.
SYNCOUT is
synchronize the chopping frequency of the PGA280
to the sampling frequency of the ADS1259.
Synchronizing the PGA280 to the ADS1259 places
the PGA280 chopped 1/f noise at an exact null in the
ADS1259 frequency response, where the PGA280 1/f
noise is rejected.
SYNCOUT frequency is equal to the ADS1259 clock
rate divided by 8 (fSYNCOUT = fCLK/8). The output clock
is enabled by the register bit SYNCOUT. Disabling
the output stops the clock but the output remains
actively driven low. In power-down mode, the
SYNCOUT output becomes an input. As with all
digital inputs, the pin must not be allowed to float. An
external 1MΩ pull-down resistor is recommended to
ground the input in power-down mode.
50W
External
XTAL1/CLKIN
Clock
XTAL2
Figure 45. External Clock Connection
Crystal Oscillator
The SYNCOUT clock is reset when START is
received and whenever registers CONFIG[2:0] are
changed. Connect SYNCOUT to the PGA280
SYNCIN pin through a 4.7kΩ series resistor. Place
the resistor as close as possible to the ADS1259
SYNCOUT pin.
Figure 46 shows the crystal oscillator connection. The
crystal connects to XTAL1/CLKIN and XTAL2 and the
capacitors connect to ground. The crystal and
capacitors should be placed close to the device pins
with short, direct traces. Neither the XTAL1/CLKIN
nor the XTAL2 pins can be used to drive any other
logic. Table 5 lists the recommended crystal for the
ADS1259. If using other crystals, verify the oscillator
start-up behavior.
SLEEP MODE
SLEEP mode is started by sending the SLEEP
command. In SLEEP mode, the device enters a
reduced power state and only a minimum of circuitry
is kept active. The WAKEUP command exits the
SLEEP mode and after which 512 fCLK cycles are
counted before the ADS1259 is ready for
communication. The register settings are unaffected
in SLEEP.
XTAL1/CLKIN
C1
Crystal
(7.3728MHz)
XTAL2
C2
C1, C2: 5pF to 20pF
SLEEP does not change the RBIAS register bit. For
quick conversions after WAKEUP, keep the internal
reference bias on before entering SLEEP. Otherwise,
after exiting SLEEP mode, allow time for the
reference to settle. Alternatively, to minimize power
consumption during SLEEP, set the internal reference
bias off prior to engaging SLEEP. Note that in SLEEP
mode the SPI timeout function is disabled.
Figure 46. Crystal Connection
Table 5. Recommended Crystal
MANUFACTURER
FREQUENCY
PART NUMBER
ECS
7.3728MHz
ECS-73-18-10
BYPASS
The digital core of the ADS1259 is powered by an
internal low dropout regulator (LDO). The DVDD
supply is the LDO input and the BYPASS pin is the
LDO output. A 1mF capacitor must be connected from
the LDO output to DGND. No other load current
should be drawn from the BYPASS pin.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): ADS1259
TI [ TEXAS INSTRUMENTS ]
