ADS1259
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SBAS424C –JUNE 2009–REVISED MARCH 2010
START
When using commands to control conversions, hold
the START pin low. The ADS1259 features two
modes to control conversions: Gate Control mode
and Pulse Control mode. The mode is selected by the
PULSE register bit.
START is a digital input that controls the ADS1259
conversions. Conversions are started when START is
taken high and are stopped when START is taken
low. If START is toggled during a conversion, the
conversion is restarted. DRDY goes high when
START is taken high. Figure 49 andTable 7 show the
START timing.
Gate Control Mode (PULSE Bit = 0, Default)
Conversions begin when either the START pin is
taken high or when the START command is sent.
Conversions continue indefinitely until the START pin
is taken low or the STOP command is transmitted. As
seen in Figure 50, DRDY is forced high when the
conversion starts and falls low when data are ready.
When stopped, the conversion in process completes
and further conversions are halted. Figure 49 and
Table 7 show the timing of DRDY and START.
Note that reasserting START within 22 tCLK cycles of
the DRDY falling edge causes DRDY to fall soon
after. This conversion result should be discarded. The
next DRDY falling edge, as given in Table 9, is the
valid conversion data.
tSDSU
tSTDR
DRDY
tPWH
tDSHD
START
or
START Pin
tPWL
STOP
or
START
or
Command(1)
START
STOP
START
Command(1)
STOP
(1) START and STOP commands take effect on the seventh SCLK
falling edge.
Converting
Halted
Halted
Figure 49. START to DRDY Timing
DRDY
CONVERSION CONTROL
(1) START and STOP opcode commands take effect on the
seventh SCLK falling edge.
The conversions of the ADS1259 are controlled by
either the START pin or by the START command.
Figure 50. Gate Control Mode
Table 7. START Timing (See Figure 49)
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
START pin low or STOP opcode to DRDY setup time to halt further
conversions
tSDSU
16
tCLK
START pin low or STOP opcode hold time to complete current
conversion (gate mode)
tDSHD
16
4
tCLK
tPWH, L
tSTDR
START pin pulse width high, low
tCLK
tCLK
START pin rising edge to DRDY rising edge
4
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