ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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RESET/PWDN
RESET
The RESET/PWDN pin has two functions: device
power-down and device reset. Momentarily holding
the pin low resets the device and holding the pin low
for 216 fCLK cycles activates the Power-Down mode.
There are three methods to reset the ADS1259: cycle
the power supplies, take RESET/PWDN low, or send
the RESET opcode command.
When using the RESET/PWDN pin, take it low to
force a reset. Make sure to follow the minimum pulse
width timing specifications before taking the RESET
pin back high.
POWER-DOWN MODE
In power-down mode, internal circuit blocks are
disabled (including the oscillator, reference, and SPI)
and the device enters a micro-power state. To
engage power-down mode, hold the RESET/PWDN
pin low for 216 fCLK cycles. Note that the register
contents are not saved because they are reset when
RESET/PWDN goes high.
The RESET command takes effect on the eighth
falling SCLK edge of the opcode command. On reset,
the configuration registers are initialized to the default
states and the conversion cycle restarts. After reset,
allow eight fCLK cycles before communicating to the
ADS1259. Note that when using the reset command,
the SPI interface itself may require reset before
accepting the command. See the SPI Timing
Characteristics section for details.
Keep the digital inputs at defined VIH or VINL logic
levels (do not 3-state). To minimize power-supply
leakage current, disable the external clock. Note that
the ADS1259 digital outputs remain active in
power-down. The analog signal inputs may float.
POWER-ON SEQUENCE
To exit power-down, take RESET/PWDN high. Wait
216 fCLK cycles before communicating to the
ADS1259, as shown in Figure 47.
The ADS1259 has three power supplies: AVDD,
AVSS, and DVDD. The supplies can be sequenced in
any order but be sure that at any time the analog
inputs do not exceed AVDD or AVSS and the digital
inputs do not exceed DVDD. After the last power
supply has crossed the respective power-on
threshold, 216 fCLK cycles are counted before
releasing the internal reset. After the internal reset is
released, the ADS1259 is ready for operation.
Figure 48 shows the power-on sequence of the
ADS1259.
tLOW
RESET/PWDN
tRHSC
SCLK
Figure 47. RESET/PWDN Timing
Table 6. Timing Characteristics for Figure 47
SYMBOL
tLOW
DESCRIPTION
Pulse width low for reset
MIN
UNIT
tCLK
tCLK
tCLK
tCLK
4
216
tLOW
Pulse width low for power-down
Reset high to SPI communication start
Exit power-down to SPI communication start
tRHSC
tRHSC
8
216
3.5V nom
AVDD - AVSS
1V nom
DVDD
CLK
216 ´ tCLK
ADS1259 Operational
Internal Reset
Figure 48. Power-On Sequence
22
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