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PCM9211 参数 Datasheet PDF下载

PCM9211图片预览
型号: PCM9211
PDF下载: 下载PDF文件 查看货源
内容描述: 216千赫数字音频接口收发器( DIX )与立体声ADC和路由 [216-kHz Digital Audio Interface Transceiver (DIX) with Stereo ADC and Routing]
分类和应用:
文件页数/大小: 121 页 / 1385 K
品牌: TI [ TEXAS INSTRUMENTS ]
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PCM9211  
www.ti.com  
SBAS495 JUNE 2010  
PLL Clock Source (Built-in PLL and VCO) Details  
The PCM9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock  
from the S/PDIF input signal.  
The VCO-derived clock is identified as the PLL clock source.  
When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When  
unlocked, the PLL generates its own free-run clock (from the VCO).  
The generated system clocks from the PLL can be set to fixed multiples of the input S/PDIF frequency. Register  
30h/PSCK[2:0] can configure the output clock to 128fS, 256fS or 512fS.  
The PCM9211 also has an automatic default output rate that is calculated based on the incoming S/PDIF  
frequency. This calculation and rate are controlled by Register 30h/PSCKAUTO. In its default mode, the SCK  
dividing ratio is configured according to these parameters:  
512fS: 54 kHz and below.  
256fS: 54 kHz to 108 kHz  
128fS: 108 kHz and above (or unlocked)  
PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when  
the PSCKAUTO Register is set to '0'.  
The PCM9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all  
PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and  
PSCK[2:0] selection is shown in Table 4.  
Table 4. SCKO, BCKO and LRCKO Frequency Set by PSCK[2:0]  
OUTPUT CLOCK AT PLL SOURCE  
PSCK[2:0] SETTING  
SCKO  
BCKO  
64fS  
LRCKO  
PSCK2  
PSCK1  
PSCK0  
128fS  
256fS  
fS  
fS  
fS  
0
0
1
0
1
0
0
0
0
64fS  
(1)  
512fS  
64fS  
(1) 512fS SCK is only supported at 108 kHz or lower sampling frequency of incoming biphase signal.  
In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.  
The relationship between the sampling frequencies (fS) of the input S/PDIF signal and the frequency of LRCKO,  
BCKO, and SCKO are shown in Table 5.  
Table 5. Output Clock Frequency at PLL Lock State  
LRCK  
fS  
BCK  
SCK (Depends on PSCK[2:0] Setting)  
256fS 512fS  
64fS  
128fS  
8 kHz  
0.512 MHz  
0.7056 MHz  
0.768 MHz  
1.024 MHz  
1.4112 MHz  
1.536 MHz  
2.048 MHz  
2.8224 MHz  
3.072 MHz  
4.096 MHz  
5.6448 MHz  
6.144 MHz  
8.192 MHz  
11.2896 MHz  
12.288 MHz  
1.024MHz  
2.048 MHz  
2.8224 MHz  
3.072 MHz  
4.096 MHz  
5.6448 MHz  
6.144 MHz  
8.192 MHz  
11.2896 MHz  
12.288 MHz  
16.384 MHz  
22.5792 MHz  
24.576 MHz  
32.768 MHz  
45.1584 MHz  
49.152 MHz  
N/A  
11.025 kHz  
12 kHz  
1.4112 MHz  
1.536 MHz  
2.048 MHz  
2.8224 MHz  
3.072 MHz  
4.096 MHz  
5.6448 MHz  
6.144 MHz  
8.192 MHz  
11.2896 MHz  
12.288 MHz  
16.384 MHz  
22.5792 MHz  
24.576 MHz  
16 kHz  
4.096 MHz  
22.05 kHz  
24 kHz  
5.6448 MHz  
6.144 MHz  
32 kHz  
8.192 MHz  
44.1 kHz  
48 kHz  
11.2896 MHz  
12.288 MHz  
16.384 MHz  
22.5792 MHz  
24.576 MHz  
32.768 MHz  
45.1584 MHz  
49.152 MHz  
64 kHz  
88.2 kHz  
96 kHz  
128 kHz  
176.4 kHz  
192 kHz  
N/A  
N/A  
Copyright © 2010, Texas Instruments Incorporated  
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Product Folder Link(s): PCM9211  
 
 
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