PCM9211
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SBAS495 –JUNE 2010
Register 79h, GPIO I/O Direction Control for MPIO_A, MPIO_B
(Address: 79h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
GIOB3DIR
0
B6
GIOB2DIR
0
B5
GIOB1DIR
0
B4
GIOB0DIR
0
B3
GIOA3DIR
0
B2
GIOA2DIR
0
B1
B0
GIOA1DIR
0
GIOA0DIR
0
GIOB3DIR: MPIO_B3 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB2DIR: MPIO_B2 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB1DIR: MPIO_B1 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB0DIR: MPIO_B0 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA3DIR: MPIO_A3 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA2DIR: MPIO_A2 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA`DIR: MPIO_A1 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA0DIR: MPIO_A0 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
These registers are effective only at MPIO_A and MPIO_B assigned as GPIO. I/O direction setting is available by
pin.
Copyright © 2010, Texas Instruments Incorporated
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