PCM9211
SBAS495 –JUNE 2010
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Register 76h, MPIO_C1, MPIO_C0 Output Flag Select
(Address: 76h, Write and Read)
DATA
B7
B6
MPC1FLG2
0
B5
MPC1FLG1
0
B4
MPC1FLG0
0
B3
MPC0FLG3
0
B2
MPC0FLG2
0
B1
MPC0FLG1
0
B0
MPC0FLG0
0
Reg Name
Default Value
Memo
MPC1FLG3
0
MPC1FLG[3:0]: MPIO_C1 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPC0FLG[3:0]: MPIO_C0 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPCSEL[2:0] = '011', MPC1SEL = '0', and MPC0SEL = '0'.
108
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