PCM9211
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SBAS495 –JUNE 2010
Register 7Bh, GPIO Output Data Setting for MPIO_A, MPIO_B
(Address: 7Bh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
GPOB3
0
B6
GPOB2
0
B5
GPOB1
0
B4
GPOB0
0
B3
GPOA3
0
B2
GPOA2
0
B1
GPOA1
0
B0
GPOA0
0
GPOB3: MPIO_B3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB2: MPIO_B2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB1: MPIO_B1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB0: MPIO_B0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA3: MPIO_A3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA2: MPIO_A2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA1: MPIO_A1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA0: MPIO_A0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
These registers are effective only as GPIOs are assigned to output.
Copyright © 2010, Texas Instruments Incorporated
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