Table 4−8. System Control Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
CardBus reserved terminals signaling. When this bit is set, the RSVD CardBus terminals are driven
low when a CardBus card has been inserted. When this bit is low, these signals are placed in a
high-impedance state.
22 ‡
CBRSVD
RW
0 = Place the CardBus RSVD terminals in a high-impedance state.
1 = Drive the CardBus RSVD terminals low (default).
V
protection enable. This bit is socket dependent.
CC
0 = V
21 ‡
VCCPROT
RSVD
RW
RW
protection is enabled for 16-bit cards (default).
protection is disabled for 16-bit cards.
CC
CC
1 = V
20−16 ‡
These bits are reserved. Do not change the value of these bits.
Memory read burst enable downstream. When this bit is set, the PCI6x21/PCI6x11 controller allows
memory read transactions to burst downstream.
15 ‡§
14 ‡§
MRBURSTDN
MRBURSTUP
RW
RW
0 = MRBURSTDN downstream is disabled.
1 = MRBURSTDN downstream is enabled (default).
Memory read burst enable upstream. When this bit is set, the PCI6x21/PCI6x11 controller allows
memory read transactions to burst upstream.
0 = MRBURSTUP upstream is disabled (default).
1 = MRBURSTUP upstream is enabled.
Socket activity status. When set, this bit indicates access has been performed to or from a PC Card.
Reading this bit causes it to be cleared. This bit is socket dependent.
0 = No socket activity (default)
13 ‡
12
SOCACTIVE
RSVD
R
R
1 = Socket activity
Reserved. This bit returns 1 when read.
Power-stream-in-progress status bit. When set, this bit indicates that a power stream to the power
switch is in progress and a powering change has been requested. When this bit is cleared, it indicates
that the power stream is complete.
11 ‡
10 †
9 †
PWRSTREAM
DELAYUP
R
R
R
0 = Power stream is complete, delay has expired (default).
1 = Power stream is in progress.
Power-up delay-in-progress status bit. When set, this bit indicates that a power-up stream has been
sent to the power switch, and proper power may not yet be stable. This bit is cleared when the power-up
delay has expired.
0 = Power-up delay has expired (default).
1 = Power-up stream sent to switch. Power might not be stable.
Power-down delay-in-progress status bit. When set, this bit indicates that a power-down stream has
been sent to the power switch, and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
DELAYDOWN
0 = Power-down delay has expired (default).
1 = Power-down stream sent to switch. Power might not be stable.
Interrogation in progress. When set, this bit indicates an interrogation is in progress, and clears when
the interrogation completes. This bit is socket-dependent.
0 = Interrogation not in progress (default)
8 †
7
INTERROGATE
RSVD
R
R
1 = Interrogation in progress
Reserved. This bit returns 0 when read.
Power savings mode enable. When this bit is set, the PCI6x21/PCI6x11 controller consumes less
power with no performance loss. This bit is shared between the two PCI6x21/PCI6x11 CardBus
functions.
6 ‡§
5 ‡§
PWRSAVINGS
SUBSYSRW
RW
RW
0 = Power savings mode disabled
1 = Power savings mode enabled (default)
Subsystem ID and subsystem vendor ID, ExCA ID and revision register read/write enable. This bit also
controls read/write for the function 3 subsystem ID register.
0 = Registers are read/write.
1 = Registers are read-only (default).
†
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
One or more bits in this register are cleared only by the assertion of GRST.
‡
§
These bits are global in nature and must be accessed only through function 0.
4−19
TI [ TEXAS INSTRUMENTS ]
