Table 4−6. Interrupt Pin Register Cross Reference
INTRTIE BIT
(BIT 29,
OFFSET 80h) OFFSET 80h)
TIEALL BIT
(BIT 28,
INTPIN
INTPIN
INTPIN
FUNCTION 3
(FLASH MEDIA)
INTPIN
Function 4
(SD Host)
INTPIN
Function 5
(Smart Card)
FUNCTION 0 FUNCTION 1
(CARDBUS)
(CARDBUS)
Determined by bits
6−5 (INT_SEL field) in 6−5 (INT_SEL field) in 6−5 (INT_SEL field) in
Determined by bits
Determined by bits
0
0
01h (INTA)
02h (INTB)
flash media general
control register (see
Section 7.21)
SD host general
control register (see
Section 8.22)
Smart Card general
control register (see
Section 9.22)
1
0
1
01h (INTA)
01h (INTA)
01h (INTA)
01h (INTA)
X
01h (INTA)
0x01 (INTA)
0x01 (INTA)
4.25 Bridge Control Register
The bridge control register provides control over various PCI6x21/PCI6x11 bridging functions. Some bits in this
register are global in nature and must be accessed only through function 0. See Table 4−7 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Bridge control
R
0
R
0
R
0
R
0
R
0
RW
0
RW
1
RW
1
RW
0
RW
1
RW
0
R
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Bridge control
3Eh (Function 0, 1)
Read-only, Read/Write
0340h
Default:
Table 4−7. Bridge Control Register Description
FUNCTION
BIT
SIGNAL
TYPE
15−11
RSVD
R
These bits return 0s when read.
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket
dependent and is not shared between functions 0 and 1.
10
9
POSTEN
PREFETCH1
PREFETCH0
INTR
RW
RW
RW
RW
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
socket dependent. This bit is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
socket dependent. This bit is encoded as:
8
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
PCI interrupt − IREQ routing enable. This bit is used to select whether PC Card functional interrupts are
routed to PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
7
1 = Functional interrupts are routed by ExCA registers.
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted.
6 †
CRST
RW
1 = CRST is asserted (default).
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
†
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
4−15
TI [ TEXAS INSTRUMENTS ]
