Table 4−8. System Control Register Description (continued)
BIT
4 ‡§
3 ‡§
2 ‡
SIGNAL
CB_DPAR
RSVD
TYPE
RW
R
FUNCTION
CardBus data parity SERR signaling enable.
0 = CardBus data parity not signaled on PCI SERR signal (default)
1 = CardBus data parity signaled on PCI SERR signal
Reserved. This bit returns 0 when read.
ExCA power control bit.
0 = Enables 3.3 V (default)
1 = Enables 5 V
EXCAPOWER
R
Keep clock. When this bit is set, the PCI6x21/PCI6x11 controller follows the CLKRUN protocol to
maintain the system PCLK and the CCLK (CardBus clock). This bit is global to the PCI6x21/PCI6x11
functions.
0 = Allow system PCLK and CCLK clocks to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
1 ‡§
KEEPCLK
RW
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI6x21/PCI6x11 controller, setting this bit maintains both the PCI clock and the CCLK.
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (R03).
When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the RI_OUT signal is routed to the
PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control register is 0, then the output
is placed in a high-impedance state. This terminal is encoded as:
0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1.
(default)
0 ‡§
RIMUX
RW
1 = PME signal is routed to the PME/RI_OUT terminal of the PCI6x21/PCI6x11 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.38) is
0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state.
‡
§
One or more bits in this register are cleared only by the assertion of GRST.
These bits are global in nature and must be accessed only through function 0.
4.30 MC_CD Debounce Register
This register provides debounce time in units of 2 ms for the MC_CD signal on UltraMedia cards. This register defaults
to 19h, which gives a default debounce time of 50 ms. All bits in this register are reset by GRST only.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
MC_CD debounce
RW
0
RW
0
RW
0
RW
1
RW
1
RW
0
RW
0
RW
1
Register:
Offset:
Type:
MC_CD debounce
84h (Functions 0, 1)
Read/Write
Default:
19h
4−20
TI [ TEXAS INSTRUMENTS ]
