Table 4−7. Bridge Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Master abort mode. This bit controls how the PCI6x21/PCI6x11 controller responds to a master abort when
the PCI6x21/PCI6x11 controller is an initiator on the CardBus interface. This bit is common between each
socket.
5
MABTMODE
RW
0 = Master aborts not reported (default).
1 = Signal target abort on PCI and signal SERR, if enabled.
4
3
RSVD
R
This bit returns 0 when read.
VGA enable. This bit affects how the PCI6x21/PCI6x11 controller responds to VGA addresses. When this
bit is set, accesses to VGA addresses are forwarded.
VGAEN
RW
ISA mode enable. This bit affects how the PCI6x21/PCI6x11 controller passes I/O cycles within the
64-Kbyte ISA range. This bit is not common between sockets. When this bit is set, the PCI6x21/PCI6x11
controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
2
1
ISAEN
RW
RW
CSERR enable. This bit controls the response of the PCI6x21/PCI6x11 controller to CSERR signals on
the CardBus bus. This bit is separate for each socket.
CSERREN
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR.
CardBus parity error response enable. This bit controls the response of the PCI6x21/PCI6x11 to CardBus
parity errors. This bit is separate for each socket.
0
CPERREN
RW
0 = CardBus parity errors are ignored (default).
1 = CardBus parity errors are reported using CPERR.
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0, this register is read/write; when bit 5
is 1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem vendor ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem vendor ID
40h (Functions 0, 1)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
Default:
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0, this register is read/write; when bit 5 is
1, this register is read-only. The default mode is read-only. All bits in this register are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Subsystem ID
42h (Functions 0, 1)
Read-only, (Read/Write when bit 5 in the system control register is 0)
0000h
Default:
4−16
TI [ TEXAS INSTRUMENTS ]
