4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI6x21/PCI6x11 controller, in units of PCI clock cycles.
When the PCI6x21/PCI6x11 controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting
from zero. If the latency timer expires before the PCI6x21/PCI6x11 transaction has terminated, then the
PCI6x21/PCI6x11 controller terminates the transaction when its GNT is deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Latency timer
0Dh
Read/Write
00h
Default:
4.10 Header Type Register
The header type register returns 82h when read, indicating that the PCI6x21/PCI6x11 functions 0 and 1 configuration
spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers
00h−7Fh, and 80h−FFh is user-definable extension registers.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
1
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Header type
0Eh (Functions 0, 1)
Read-only
Default:
82h
4.11 BIST Register
Because the PCI6x21/PCI6x11 controller does not support a built-in self-test (BIST), this register returns the value
of 00h when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
BIST
0Fh (Functions 0, 1)
Read-only
Default:
00h
4−7
TI [ TEXAS INSTRUMENTS ]
