4.14 Secondary Status Register
The secondary status register is compatible with the PCI-PCI bridge secondary status register. It indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (PCI
offset 06h, see Section 4.5), and status bits are cleared by a writing a 1. This register is not shared by the two socket
functions, but is accessed on a per-socket basis. See Table 4−5 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Secondary status
RC
0
RC
0
RC
0
RC
0
RC
0
R
0
R
1
RC
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Secondary status
16h
Read-only, Read/Clear
0200h
Default:
Table 4−5. Secondary Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
Detected parity error. This bit is set when a CardBus parity error is detected, either an address or data
parity error. Write a 1 to clear this bit.
15 ‡
CBPARITY
RC
Signaled system error. This bit is set when CSERR is signaled by a CardBus card. The PCI6x21/PCI6x11
controller does not assert the CSERR signal. Write a 1 to clear this bit.
14 ‡
13 ‡
12 ‡
11 ‡
10−9
CBSERR
CBMABORT
REC_CBTA
SIG_CBTA
CB_SPEED
RC
RC
RC
RC
R
Received master abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the
CardBus bus is terminated by a master abort. Write a 1 to clear this bit.
Received target abort. This bit is set when a cycle initiated by the PCI6x21/PCI6x11 controller on the
CardBus bus is terminated by a target abort. Write a 1 to clear this bit.
Signaled target abort. This bit is set by the PCI6x21/PCI6x11 controller when it terminates a transaction
on the CardBus bus with a target abort. Write a 1 to clear this bit.
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the
PCI6x21/PCI6x11 controller asserts this signal at a medium speed.
CardBus data parity error detected. Write a 1 to clear this bit.
0 = The conditions for setting this bit have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
8 ‡
CB_DPAR
RC
b. The PCI6x21/PCI6x11 controller was the bus master during the data parity error.
c. The parity error response enable bit (bit 0) is set in the bridge control register (PCI offset 3Eh,
see Section 4.25).
Fast back-to-back capable. The PCI6x21/PCI6x11 controller cannot accept fast back-to-back
transactions; therefore, this bit is hardwired to 0.
7
6
CBFBB_CAP
CB_UDF
R
R
User-definable feature support. The PCI6x21/PCI6x11 controller does not support user-definable
features; therefore, this bit is hardwired to 0.
66-MHz capable. The PCI6x21/PCI6x11 CardBus interface operates at a maximum CCLK frequency of
33 MHz; therefore, this bit is hardwired to 0.
5
CB66MHZ
RSVD
R
R
4−0
These bits return 0s when read.
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−9
TI [ TEXAS INSTRUMENTS ]
