Table 4−4. Status Register Description (continued)
BIT
SIGNAL
TYPE
FUNCTION
Capabilities list. This bit returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power-management capabilities is implemented in this
function.
4
CAPLIST
R
Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE) in the
command register (PCI offset 04h, see Section 4.4) is a 0 and this bit is a 1, is the function’s INTx signal
asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit.
3
INT_STATUS
RSVD
RU
R
2−0
Reserved. These bits return 0s when read.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI6x21/PCI6x11 controller.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Revision ID
08h (functions 0, 1)
Read-only
00h
Default:
4.7 Class Code Register
The class code register recognizes PCI6x21/PCI6x11 functions 0 and 1 as a bridge device (06h) and a CardBus
bridge device (07h), with a 00h programming interface.
Bit
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
PCI class code
Base class
Subclass
Programming interface
Type
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default
Register:
Offset:
Type:
PCI class code
09h (functions 0, 1)
Read-only
Default:
06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Cache line size
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Cache line size
0Ch (Functions 0, 1)
Read/Write
00h
Default:
4−6
TI [ TEXAS INSTRUMENTS ]
