Table 4−14. Multifunction Routing Status Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
0000 = GPI1
0001 = GPO1
0010 = INTB
0011 = IRQ3
0100 = OHCI_LED 1000 = CAUDPWM
1100 = LEDA1
1101 = LEDA2
1110 = GPE
7−4 ‡
MFUNC1
RW
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
0001 = GPO0
0010 = INTA
0011 = IRQ3
0100 = IRQ4
0101 = IRQ5
0110 = RSVD
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LEDA1
1101 = LEDA2
1110 = GPE
3−0 ‡
MFUNC0
RW
1111 = IRQ15
‡
One or more bits in this register are cleared only by the assertion of GRST.
4.37 Retry Status Register
The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The
flags are set when the PCI6x21/PCI6x11 controller, as a master, receives a retry and does not retry the request within
15
2
clock cycles. The flags are cleared by writing a 1 to the bit. Access this register only through function 0. See
Table 4−15 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Retry status
RW
1
RW
1
RC
0
R
0
RC
0
R
0
RC
0
R
0
Register:
Offset:
Type:
Retry status
90h (Functions 0, 1)
Read-only, Read/Write, Read/Clear
C0h
Default:
Table 4−15. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
7 ‡
PCIRETRY
RW
1 = PCI retry counter enabled (default)
CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
6 ‡§
CBRETRY
RW
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
5 ‡
4
TEXP_CBB
RSVD
RC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
3 ‡§
2
TEXP_CBA
RSVD
RC
R
1 = Retry has expired.
Reserved. This bit returns 0 when read.
PCI target retry expired. Write a 1 to clear this bit.
1 ‡
0
TEXP_PCI
RSVD
RC
R
0 = Inactive (default)
1 = Retry has expired.
Reserved. This bit returns 0 when read.
‡
§
One or more bits in this register are cleared only by the assertion of GRST.
These bits are global in nature and must be accessed only through function 0.
4−26
TI [ TEXAS INSTRUMENTS ]
