5.29 Hot Swap Control Status Register
The hot swap control status register contains control and status information for CPCI hot swap resources. See
Table 5–22 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Hot swap control status
R/C/U
0
R/C/U
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
Register:
Type:
Hot swap control status
Read-only, Read/Write
Offset:
Default:
E6h
00h
Table 5–22. Hot Swap Control Status Register
BIT
TYPE
FUNCTION
ENUM insertion status. When set, the ENUM output is driven by the PCI2250. This bit defaults to 0, and will be set after
R/C/U a PCI reset occurs, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set following an insertion when the board
implementing the PCI2250 is ready for configuration. This bit cannot be set under software control.
7
ENUM extraction status. When set, the ENUM output is driven by the PCI2250. This bit defaults to 0, and is set when the
R/C/U ejectorhandleisopenedandbit7is0. Thus, thisbitissetwhentheboardimplementingthePCI2250isabouttoberemoved.
This bit cannot be set under software control.
6
5–4
R
Reserved. Bits 5 and 4 return 0s when read.
LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions. However,
for a duration following a PCI_RST, the HSLED output is driven high by the PCI2250 and this bit is ignored. When this bit
is interpreted, a 1 will cause HSLED high and a 0 will cause HSLED low.
3
R/W
Following PCI_RST, the HSLED output is driven high by the PCI2250 until the ejector handle is closed. When these
conditions are met, the HSLED is under software control via this bit.
2
1
0
R
R/W
R
Reserved. Bit 2 returns 0 when read.
ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 6 and 7 are set independently
from this bit.
0 = Enable HSENUM output
1 = Mask HSENUM output
Reserved. Bit 0 returns 0 when read.
5–23
TI [ TEXAS INSTRUMENTS ]
