5.3 Arbiter Control Register
The arbiter control register is used for the bridge’s internal arbiter. The arbitration scheme used is a two-tier rotational
arbitration. The PCI2250 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Arbiter control
R
0
R
0
R
0
R
0
R
0
R
0
R/W
1
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Arbiter control
Read-only, Read/Write
Offset:
Default:
42h
0200h
Table 5–3. Arbiter Control Register
BIT
TYPE
FUNCTION
15–10
R
Reserved. Bits 15–10 return 0s when read.
Bridge tier select. This bit determines in which tier the bridge is placed in the two-tier arbitration scheme.
9
8–4
3
R/W
R
0 = Lowest priority tier
1 = Highest priority tier (default)
Reserved. Bits 8–4 return 0s when read.
GNT3 tier select. This bit determines in which tier the S_GNT3 is placed in the arbitration scheme. This bit is encoded as:
R/W
0 = Lowest priority tier (default)
1 = Highest priority tier
GNT2 tier select. This bit determines in which tier the S_GNT2 is placed in the arbitration scheme. This bit is encoded as:
2
1
0
R/W
R/W
R/W
0 = Lowest priority tier (default)
1 = Highest priority tier
GNT1 tier select. This bit determines in which tier the S_GNT1 is placed in the arbitration scheme. This bit is encoded as:
0 = Lowest priority tier (default)
1 = Highest priority tier
GNT0 tier select. This bit determines in which tier the S_GNT0 is placed in the arbitration scheme. This bit is encoded as:
0 = Lowest priority tier (default)
1 = Highest priority tier
5–3
TI [ TEXAS INSTRUMENTS ]
