4.26 I/O Base Upper 16 Bits Register
The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address
that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base upper 16 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
I/O base upper 16 bits
Read/Write
30h
0000h
4.27 I/O Limit Upper 16 Bits Register
The I/O limit upper 16-bits register specifies the upper 16 bits corresponding to AD31–AD16 of the 32-bit address
that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
I/O limit upper 16 bits
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
I/O limit upper 16 bits
Read/Write
32h
0000h
4.28 Capability Pointer Register
ThecapabilitypointerregisterprovidesthepointertothePCIconfigurationheaderwherethePCIpowermanagement
register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The
capability pointer register is read-only and returns DCh when read, indicating the power management registers are
located at PCI header offset DCh.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Capability pointer register
R
1
R
1
R
0
R
1
R
1
R
1
R
0
R
0
Register:
Type:
Offset:
Default:
capability pointer
Read-only
34h
DCh
4–13
TI [ TEXAS INSTRUMENTS ]
