4.17 I/O Base Register
The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O
addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to
address bits AD15–AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of
the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base
address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.26).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
I/O base
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
1
Register:
Type:
I/O base
Read-only, read/write
Offset:
Default:
1Ch
01h
4.18 I/O Limit Register
The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O
addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to
address bits AD15–AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of
the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit
address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.27).
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
I/O limit
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
1
Register:
Type:
I/O limit
Read-only, read/write
Offset:
Default:
1Dh
01h
4–9
TI [ TEXAS INSTRUMENTS ]
