4.8 Primary Latency Timer Register
The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is
aprimaryPCIbusinitiatorandassertsP_FRAME, thelatencytimerbeginscountingfrom0. Ifthelatencytimerexpires
before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is
deasserted.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Latency timer
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Register:
Type:
Offset:
Default:
Latency timer
Read/write
0Dh
00h
4.9 Header Type Register
The header type register is read-only and returns 01h when read, indicating that the PCI2250 configuration space
adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h–3Fh of configuration space is
considered.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Header type
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
Register:
Type:
Offset:
Default:
Header type
Read-only
0Eh
01h
4.10 BIST Register
The PCI2250 does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when
read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
BIST
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
BIST
Read-only
0Fh
00h
4–6
TI [ TEXAS INSTRUMENTS ]
