OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
Acronym
EECR
EESR
SER
Register Description
Event Enable Clear Register
Event Enable Set Register
0x01C0 2228
0x01C0 2230
0x01C0 2238
Secondary Event Register
0x01C0 2240
SECR
IER
Secondary Event Clear Register
Interrupt Enable Register
0x01C0 2250
0x01C0 2258
IECR
IESR
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
0x01C0 2260
0x01C0 2268
IPR
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
0x01C0 2280
0x01C0 2284
QEER
QEECR
QEESR
QSER
QSECR
—
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 4000 - 0x01C0 4FFF
Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers
Offset
Transfer Controller Transfer Controller
Acronym
Register Description
0
1
BYTE ADDRESS
BYTE ADDRESS
0h
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8288
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
0x01C0 8688
PID
Peripheral Identification Register
4h
TCCFG
EDMA3TC Configuration Register
EDMA3TC Channel Status Register
Error Status Register
100h
120h
124h
128h
12Ch
130h
140h
240h
244h
248h
24Ch
250h
254h
258h
25Ch
260h
280h
284h
288h
TCSTAT
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
SASRC
Source Active Source Address Register
Source Active Count Register
SACNT
SADST
Source Active Destination Address Register
Source Active B-Index Register
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
DFCNTRLD
DFSRCBREF
DFDSTBREF
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Destination FIFO Set Count Reload Register
Destination FIFO Set Source Address B-Reference Register
Destination FIFO Set Destination Address B-Reference
Register
300h
304h
308h
30Ch
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
DFOPT0
DFSRC0
DFCNT0
DFDST0
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
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Peripheral Information and Electrical Specifications
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